James Clerk Maxwell Foundation

http://www.clerkmaxwellfoundation.org/index.html

opening a chinese document saved in windows partition with gedit

在Applications菜单上点右键，选择Edit Menu.在Main Menu的对话框中勾选System Tools－－Configuration Editor，并从Applications菜单中开启。

依次开启 /apps/gedit-2/preferences/encodings/双击右侧auto_detected,在弹出对话框中点选Add，添加Values值为GB18030,确定后选中，点选Up按钮将其移至第一位。

同样方法，对show_in_menu进行设置，并将GB18030置于首位。

trigonometry

trigonometry: 三角学

long lines in spice

All file lines must start in the first (left-most) column. When a line is too long to fit, break the line and use the + symbol as the first character of the extension line.
(The maximum length of a line is 132 Characters)

Bluetooth Setup in Ubuntu

https://help.ubuntu.com/community/BluetoothSetup

for me, whenever I want to connect my cordless mouse, do the following two steps:
1. sudo /etc/init.d/bluetooth restart
2. sudo hidd --search

get the system properties in matlab

For example, we have a state space system called "demo", in order to get the A, B, C, D matrices of that system, there are two ways:

1. get(demo, 'A'), get(demo, 'B')...get(demo,'D')
2. demo.A, demo.B, demo.C, demo.D

simulation when lpm_ram_dq is used

When lpm_ram_dq is used to create memory, the simulation provided by Quartus II doesn't work any more.

high impedance in vhdl

Although vhdl is case insensitive, when it comes to high impedance, "Z" must be used instead of "z".

microcomputer design

load: 1,3
-- load register 3 with the memory data whose address is stored in register 1.

store: 2,4
-- put the data stored in register 2 into the memory address stored in register 4.

brgtI: 1,7, 58
-- branch to memory 58 if data stored in register 1 is greater that register 7.

VHDL Notes

1) .acf: pin assignment and configuration file
2) .mif: memory initialization file

3) LPM Components

Altera MAX+PlusII contains a Library of Parameterized Modules(LPM) that allows implementation of devices such as RAM, ROM, arithmetic devices, etc. The size of the devices are parameterized. That is, the number of bits in the operands are specified at the time an instance of the component is made. In order to use these components, you must declare the LPM library(LIBRARY lpm;) and specify which package to use in this library(USE lpm.lpm_components.all;). The following example shows how to use a LPM add/subtract device to create a 32-bit add/subtract unit.

LPM Example

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY add_subt IS
PORT(a, b: IN std_logic_vector(31 downto 0);
a_s: IN std_logic;
answer: OUT std_logic_vector(31 downto 0));
END add_subt;
ARCHITECTURE struct OF add_subt IS
BEGIN
-- u1 is an arbitrary name of the instance
u1: lpm_add_sub -- This is the name of the component
GENERIC MAP(lpm_width => 32)
-- data, datab, add_sub, result are the formal parameter names
PORT MAP( dataa => a, datab => b, add_sub => a_s,
result => answer);
END struct;

A list of LPM components is available using HELP-> megafunctions/LPM in Altera MAX+PlusII.

Initial values of variables and signals in VHDL

Initial values when declaring a signal can only be used in simulation and will be ignored in synthesis.

Initial values when declaring a variable may be ignored in synthesis, as far as I know.

s domain transfer function to z domain

functions that are frequently used:
1.tf
2.poly & roots
3.c2d
4.zpk

Example:
>> sys=tf(0.1, poly([0 -0.1]))

Transfer function:
0.1
-----------
s^2 + 0.1 s

>> zsys=c2d(sys,1,'zoh')

Transfer function:
0.04837 z + 0.04679
----------------------
z^2 - 1.905 z + 0.9048

Sampling time: 1
>> zsys_zpk=zpk(zsys)

Zero/pole/gain:
0.048374 (z+0.9672)
-------------------
(z-1) (z-0.9048)

Sampling time: 1

a program that some day I will look back on

library ieee;
use ieee.std_logic_1164.all;

entity test is
port(clk: in std_logic;
qout: out std_logic_vector(7 downto 0));
end test;

architecture behavior of test is
begin
process(clk)
variable A: std_logic_vector(7 downto 0):="01111111"; --so that 0 will run

begin
if(clk 'event and clk='1')then
A:=A(6 downto 0)& A(7);
end if;
qout<=A;
end process;

end behavior;

VHDL References and Tutorials

IEEE Standard VHDL Language Reference Manual:
http://media.edt.hist.no/dig-sys/VHDL-standarden/1076_toc.htm

convert transfer functions between s domain and z domain

s->z: use function "c2d"

z->s: use function "d2c"

resampling: "d2d"

VHDL on mac

http://epicentertech.biz/services/mac_eda/index.html

http://www.csee.umbc.edu/help/VHDL/index.shtml#cadence

http://ghdl.free.fr/

Extract several pages from one pdf file using pdftk

For example, I want to extract page 32 to page 86 from file 'test.pdf', resulting a 'new.pdf'. A 'cat' operation will be used to tackle this problem.

The example given in the official website is as such:

Split Select Pages from Multiple PDFs into a New Document
pdftk A=one.pdf B=two.pdf cat A1-7 B1-5 A8 output combined.pdf


My solution based on that is:
pdftk A=test.pdf cat A32-86 output new.pdf

Relationship between dB and dBm