a program that some day I will look back on

library ieee;
use ieee.std_logic_1164.all;

entity test is
port(clk: in std_logic;
qout: out std_logic_vector(7 downto 0));
end test;

architecture behavior of test is
begin
process(clk)
variable A: std_logic_vector(7 downto 0):="01111111"; --so that 0 will run

begin
if(clk 'event and clk='1')then
A:=A(6 downto 0)& A(7);
end if;
qout<=A;
end process;

end behavior;