VHDL Notes

1) .acf: pin assignment and configuration file
2) .mif: memory initialization file

3) LPM Components

Altera MAX+PlusII contains a Library of Parameterized Modules(LPM) that allows implementation of devices such as RAM, ROM, arithmetic devices, etc. The size of the devices are parameterized. That is, the number of bits in the operands are specified at the time an instance of the component is made. In order to use these components, you must declare the LPM library(LIBRARY lpm;) and specify which package to use in this library(USE lpm.lpm_components.all;). The following example shows how to use a LPM add/subtract device to create a 32-bit add/subtract unit.

LPM Example

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY add_subt IS
PORT(a, b: IN std_logic_vector(31 downto 0);
a_s: IN std_logic;
answer: OUT std_logic_vector(31 downto 0));
END add_subt;
ARCHITECTURE struct OF add_subt IS
BEGIN
-- u1 is an arbitrary name of the instance
u1: lpm_add_sub -- This is the name of the component
GENERIC MAP(lpm_width => 32)
-- data, datab, add_sub, result are the formal parameter names
PORT MAP( dataa => a, datab => b, add_sub => a_s,
result => answer);
END struct;

A list of LPM components is available using HELP-> megafunctions/LPM in Altera MAX+PlusII.

Initial values of variables and signals in VHDL

Initial values when declaring a signal can only be used in simulation and will be ignored in synthesis.

Initial values when declaring a variable may be ignored in synthesis, as far as I know.

s domain transfer function to z domain

functions that are frequently used:
1.tf
2.poly & roots
3.c2d
4.zpk

Example:
>> sys=tf(0.1, poly([0 -0.1]))

Transfer function:
0.1
-----------
s^2 + 0.1 s

>> zsys=c2d(sys,1,'zoh')

Transfer function:
0.04837 z + 0.04679
----------------------
z^2 - 1.905 z + 0.9048

Sampling time: 1
>> zsys_zpk=zpk(zsys)

Zero/pole/gain:
0.048374 (z+0.9672)
-------------------
(z-1) (z-0.9048)

Sampling time: 1

a program that some day I will look back on

library ieee;
use ieee.std_logic_1164.all;

entity test is
port(clk: in std_logic;
qout: out std_logic_vector(7 downto 0));
end test;

architecture behavior of test is
begin
process(clk)
variable A: std_logic_vector(7 downto 0):="01111111"; --so that 0 will run

begin
if(clk 'event and clk='1')then
A:=A(6 downto 0)& A(7);
end if;
qout<=A;
end process;

end behavior;

VHDL References and Tutorials

IEEE Standard VHDL Language Reference Manual:
http://media.edt.hist.no/dig-sys/VHDL-standarden/1076_toc.htm

convert transfer functions between s domain and z domain

s->z: use function "c2d"

z->s: use function "d2c"

resampling: "d2d"

VHDL on mac

http://epicentertech.biz/services/mac_eda/index.html

http://www.csee.umbc.edu/help/VHDL/index.shtml#cadence

http://ghdl.free.fr/