Initial values when declaring a signal can only be used in simulation and will be ignored in synthesis.

Initial values when declaring a variable may be ignored in synthesis, as far as I know.

## Wednesday, March 12, 2008

## Tuesday, March 11, 2008

### s domain transfer function to z domain

functions that are frequently used:

1.tf

2.poly & roots

3.c2d

4.zpk

Example:

>> sys=tf(0.1, poly([0 -0.1]))

Transfer function:

0.1

-----------

s^2 + 0.1 s

>> zsys=c2d(sys,1,'zoh')

Transfer function:

0.04837 z + 0.04679

----------------------

z^2 - 1.905 z + 0.9048

Sampling time: 1

>> zsys_zpk=zpk(zsys)

Zero/pole/gain:

0.048374 (z+0.9672)

-------------------

(z-1) (z-0.9048)

Sampling time: 1

1.tf

2.poly & roots

3.c2d

4.zpk

Example:

>> sys=tf(0.1, poly([0 -0.1]))

Transfer function:

0.1

-----------

s^2 + 0.1 s

>> zsys=c2d(sys,1,'zoh')

Transfer function:

0.04837 z + 0.04679

----------------------

z^2 - 1.905 z + 0.9048

Sampling time: 1

>> zsys_zpk=zpk(zsys)

Zero/pole/gain:

0.048374 (z+0.9672)

-------------------

(z-1) (z-0.9048)

Sampling time: 1

## Wednesday, March 5, 2008

### a program that some day I will look back on

library ieee;

use ieee.std_logic_1164.all;

entity test is

port(clk: in std_logic;

qout: out std_logic_vector(7 downto 0));

end test;

architecture behavior of test is

begin

process(clk)

variable A: std_logic_vector(7 downto 0):="01111111"; --so that 0 will run

begin

if(clk 'event and clk='1')then

A:=A(6 downto 0)& A(7);

end if;

qout<=A;

end process;

end behavior;

use ieee.std_logic_1164.all;

entity test is

port(clk: in std_logic;

qout: out std_logic_vector(7 downto 0));

end test;

architecture behavior of test is

begin

process(clk)

variable A: std_logic_vector(7 downto 0):="01111111"; --so that 0 will run

begin

if(clk 'event and clk='1')then

A:=A(6 downto 0)& A(7);

end if;

qout<=A;

end process;

end behavior;

## Saturday, March 1, 2008

### VHDL References and Tutorials

IEEE Standard VHDL Language Reference Manual:

http://media.edt.hist.no/dig-sys/VHDL-standarden/1076_toc.htm

http://media.edt.hist.no/dig-sys/VHDL-standarden/1076_toc.htm

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